An embedded interconnect (damascene) technique is effective as a method of forming multiple-layer interconnects in a semiconductor integrated circuit device. One such technique is a dual damascene technique wherein an interconnect trench in which a top-layer interconnect is formed and a via hole (or contact hole) that connects the top-layer interconnect and a bottom-layer interconnect (or substrate) are formed in an insulating film, after which the same metal film is embedded in the interconnect trench and via hole to form the interconnect and via into a unitary body. The dual damascene technique is advantageous in that manufacturing cost can be reduced greatly owing to simplification and speed-up of the manufacturing process.
A prior-art example of a method (dual hard mask method) of forming a Cu dual damascene interconnect using a 2-layer hard mask formed on a film between interconnect layers will be illustrated below with reference to FIGS. 5A-5G.
First, a first anti-reflective film [organic BARC (Bottom Anti-Reflective Coating)] 108 is formed on a semiconductor substrate obtained by successively forming a cap film 102, a via interlayer film 103, an etching stopper film 104, an interconnect interlayer film 105, a first hard mask 106 and a second hard mask 107 on a Cu bottom-layer interconnect layer 101, and a first photoresist 109 having an aperture pattern whose opening width corresponds to the width of the interconnect is formed on the first anti-reflective film 108 [see FIG. 5A]. Next, by using the first photoresist 109 as an etching mask, the first anti-reflective film 108 and second hard mask 107 are dry-etched until the first hard mask 106 is exposed, thereby forming a desired trench pattern 121 (a trench corresponding to the interconnect width). The first photoresist 109 and first anti-reflective film 108 are then removed [see FIG. 5B]. Next, a second anti-reflective film (BARC) 113 is formed on the substrate [see FIG. 5C] and a second photoresist 111 having an aperture pattern whose opening width corresponds to the diameter of the via is formed on the second anti-reflective film 113 [see FIG. 5D]. Next, by using the second photoresist 111 as an etching mask, the second anti-reflective film 113, first hard mask 106 and interconnect interlayer film 105 are dry-etched selectively until the etching stopper film 104 is exposed, thereby forming a desired trench pattern 122 (a trench corresponding to the via diameter) [see FIG. 5E], after which the second photoresist 111 and second anti-reflective film 113 are removed [see FIG. 5F]. Next, the first hard mask 106 and etching stopper film 104 are dry-etched selectively or simultaneously using the second hard mask 107 as an etching mask, then the interconnect interlayer film 105 and via interlayer film 103 are dry-etched selectively or simultaneously until the etching stopper film 104 and cap film 102 are exposed, thereby forming an interconnect trench 123 and via hole 124 [see FIG. 5G].
Next, the exposed cap film 102 is etched by the etch-back method until the Cu bottom-layer interconnect layer 101 is exposed, then the substrate where the portion of the Cu bottom-layer interconnect layer 101 is exposed is washed. Thereafter, a Cu plating film is formed on the substrate (after a seed film and metal barrier film have been formed) until the via hole and interconnect trench are filled, after which the CU plating film and metal barrier film are flattened (not shown) by CMP (Chemical Mechanical Polishing). The result is formation of a Cu dual damascene interconnect that is electrically connected with the Cu bottom-layer interconnect layer.